SPU Platform
The SPU Platform is Pinnacle’s open hardware and software R&D programme for deterministic exact arithmetic, reproducible inference, and hardware-verifiable evidence.
SPU-13
SPU-13 is the flagship platform and development system. It brings together the shared arithmetic, spatial-processing, FPGA, firmware, and verification work.
GPU and streaming rasterizer
The active development track. A graphics pipeline that generates pixels in step with the display beam and holds no framebuffer, so it consumes no external memory bandwidth. It reached silicon across three consecutive days in September 2026 — video output, rasterized geometry, then depth-resolved geometry.
It is an SPU-13 subsystem, not a separately packaged product, and it is early: no 3D, no shading, no host link. See the graphics track and Evidence.
SPU-4 Sentinel
A smaller reusable FPGA IP block for edge classification and monitoring, with its own product boundary and validation contract. Paused 3 September 2026, with active development planned; its results stand.
SOM sidecar
A deterministic inference sidecar: labeled data or sensor features enter a deterministic pipeline, and the FPGA emits a checksummed decision-evidence frame. Paused 3 September 2026 pending a retest; its results stand and remain published.