Hardware and Software R&D
Open FPGA platform development for exact arithmetic, reproducible inference, and hardware evidence.
Work in development
A deterministic exact-arithmetic FPGA platform. The active track is a GPU and streaming rasterizer that holds no framebuffer and generates pixels in step with the display beam.
SPU-13 is not presented as a finished product. The repository records what is proven, what is experimental, what is paused, and what has been retracted.
Explore SPU-13 →A framebuffer-less streaming rasterizer that generates pixels in step with the display beam, using no external memory bandwidth.
Reached silicon across three consecutive days in September 2026: video output, rasterized geometry, then depth-resolved geometry. No 3D, no shading and no host link yet.
Explore GPU and rasterizer →A smaller deterministic FPGA IP block intended for edge classification and monitoring applications.
Developed within the SPU platform with its own product boundary and validation contract. Paused 3 September 2026, with active development planned; its results stand.
Explore SPU-4 Sentinel →A writable FPGA inference sidecar that emits checksummed, bit-exact decision evidence.
Paused 3 September 2026 pending a retest. All 150 SOM1 records matched the exact software oracle on two FPGA families; those results stand and remain published.
Explore SOM sidecar →Contact
Pinnacle is currently focused on development, outreach, and promotion rather than commercial engagements.
